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S1008C3E 1008C9E
WCFS1008C3E WCFS1008C9E
128K x 8 Static RAM
Features
* High speed -- tAA = 15 ns * 2.0V Data Retention * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE1, CE2, and OE options Two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable One (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The WCFS1008C3E is available in standard 300-mil-wide SOJ. The WCFS1008C9E is available in standard 400-milwide SOJ. The WCFS1008C3E and WCFS1008C9E are functionally equivalent in all other respects..
Functional Description
The WCF1008C3E and WCFS1008C9E are high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip Enable
Logic Block Diagram
Pin Configurations
SOJ
I/O0
INPUT BUFFER
Top View
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3
A0 A1 A2 A3 A4 A5 A6 A7 A8
I/O1
ROW DECODER
I/O2
SENSE AMPS 512 x 256 x 8 ARRAY
I/O3 I/O4 I/O5
CE1 CE2 WE OE
COLUMN DECODER
POWER DOWN
I/O6 I/O7
Selection Guide
Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) WCFS1008C3E WCFS1008C9E 15ns 15 80 10
A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16
Revised April 12, 2002
WCFS1008C3E WCFS1008C9E
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND
[1]
Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA
Operating Range
Range Commercial Ambient Temperature[2] 0C to +70C VCC 5V 10%
.... -0.5V to +7.0V
DC Voltage Applied to Outputs in High Z State[1] ....................................-0.5V to VCC + 0.5V DC Input Voltage[1].................................-0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
Test Conditions Parameter VOH VOL VIH VIL IIX IOZ IOS ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current Output Short Circuit Current[3] VCC Operating Supply Current Automatic CE Power-Down Current --TTL Inputs Automatic CE Power-Down Current --CMOS Inputs GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE1 > VIH or CE2 < VIL, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE1 > VCC - 0.3V, or CE2 < 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.3 -1 -5 WCFS1008C3E WCFS1008C9E 15ns Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 -300 80 Max. Unit V V V V A A mA mA
ISB1
40
mA
ISB2
10
mA
Capacitance[ 4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 9 8 Unit pF pF
Note: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the case temperature. 3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters.
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WCFS1008C3E WCFS1008C9E
AC Test Loads and Waveforms
5V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) Equivalent to: R2 255 R1 480 R1 480 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) R2 255 GND
3 ns
ALL INPUT PULSES 3.0V 90% 10% 90% 10%
3 ns
THEVENIN EQUIVALENT 167 1.73V OUTPUT
Switching Characteristics[5] Over the Operating Range
WCFS1008C3E WCFS1008C9E-15 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE
[8]
Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid, CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z
[6, 7] [7]
Min. 15
Max.
Unit ns
15 3 15 7 0 7 3 7 0 15 15 12 12 0 0 12 8 0 3 7
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CE1 LOW to Low Z, CE2 HIGH to Low Z
CE1 HIGH to High Z, CE2 LOW to High Z[6, 7] CE1 LOW to Power-Up, CE2 HIGH to Power-Up CE1 HIGH to Power-Down, CE2 LOW to Power-Down Write Cycle Time[9] CE1 LOW to Write End, CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[7] WE LOW to High Z[6, 7]
Note: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
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WCFS1008C3E WCFS1008C9E
Data Retention Characteristics Over the Operating Range
Parameter VDR tCDR tR Description VCC for Data Retention Chip Deselect to Data Retention Time Operation Recovery Time Conditions No input may exceed VCC + 0.5V VCC = VDR = 2.0V, CE1 > VCC - 0.3V or CE2 < 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Min. 2.0 0 200 Max Unit V ns s
Data Retention Waveform
DATA RETENTION MODE VCC 4.5V tCDR CE VDR > 2V 4.5V tR
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS tRC CE1 CE2 tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE
DATA OUT
Note: 10. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
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WCFS1008C3E WCFS1008C9E
Switching Waveforms (continued)
Write Cycle No. 1 (CE1 or CE2 Controlled)[10, 14]
tWC ADDRESS tSCE CE1 tSA CE2 tSCE tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[10, 14]
tWC ADDRESS tSCE CE1
CE2 tSCE tAW tSA WE tPWE tHA
OE tSD DATA I/O NOTE 15 tHZOE
Notes: 13. Data I/O is high impedance if OE = VIH. 14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. 15. During this period the I/Os are in the output state and input signals should not be applied.
tHD
DATAIN VALID
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WCFS1008C3E WCFS1008C9E
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[14]
tWC ADDRESS tSCE CE1
CE2 tSCE tAW tSA WE tSD DATA I/O NOTE 15 tHZWE DATA VALID tLZWE tHD tPWE tHA
Truth Table
CE1 H X L L L CE2 X L H H H OE X X L X H WE X X H L H I/O0 - I/O7 High Z High Z Data Out Data In High Z Power-Down Power-Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 15 Ordering Code WCFS1008C3E-JC15 WCFS1008C9E-JC15 Package Name J J Package Type 32-Lead (300-Mil) Molded SOJ 32-Lead (400-Mil) Molded SOJ Operating Range Commercial
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WCFS1008C3E WCFS1008C9E
Package Diagrams
32-Lead (300-Mil) Molded SOJ J
32-Lead (400-Mil) Molded SOJ J
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WCFS1008C3E WCFS1008C9E
Document Title: WCFS1008C3E WCFS1008C9E 128K x 8 SRAM REV. ** Issue Date 4/12/02 Orig. of Change XFL Description of Change NEW DATASHEET
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